MediaTek MT5932 is a highly integrated chipset containing a microcontroller unit (MCU), a low power 1x1 11n single-band Wi-Fi subsystem and a power management unit (PMU). The MCU is an ARM Cortex-M4 processor with floating point unit. Visit the overview page to compare different smart home chipsets.

Key features

  • Highly integrated with RF, MCU and memory

  • Low power mode with RTC

  • Target Applications: standalone SDIO module, single-cloud connectivity

The Wi-Fi subsystem contains 802.11b/g/n radio, baseband and MAC designed for low power and high throughput application development. It also contains a 32-bit RISC CPU that could fully offload the application processor.

MT5932 also supports interfaces including UART, I2C, SPI, I2S, PWM, SDIO and ADC.

MT5932 chipset block diagram


  • IEEE 802.11 b/g/n (2.4GHz, 1x1)

  • Supports 20MHz, 40MHz bandwidth in 2.4GHz band

  • Wi-Fi security WEP/WPA2/WPS

  • Wi-Fi direct

  • SoftAP, sniffer

  • MediaTek smart connection

  • Single-cloud connectivity

  • Receiver antenna diversity

  • Integrated Balun, PA/LNA

  • Optional external LNA and PA support

Microcontroller subsystem

  • 192MHz ARM® Cortex®-M4 with FPU

  • 14 DMA channels

  • 1 RTC timer, 1 64-bit and 5 32-bit general purpose timers

  • Hardware DFS from 3MHz to 192MHz

  • Development support: SWD, JTAG

  • Crypto engine including AES, DES, MD5 and SHA-1/224/256/384/512

  • True random number generator

  • JTAG password protection


  • Up to 384KB SRAM, with zero-wait state and 96MHz maximum frequency

  • Up to 32KB L1 cache, with high hit rate, zero- wait state and 192MHz maximum frequency

Communication interfaces

  • Integrated DC-DC
  • 1 SDIO 2.0 master and 1 SDIO 2.0 slave
  • 1 I2C (3.4Mbps) interface
  • 3 UARTs (3Mbps and with hardware flow control)
  • 1 SPI master and 1 SPI slave (both SCKs are up to 48MHz, quad mode)
  • 1 SPI master for external serial flash (48MHz maximum SCK frequency, quad mode)
  • 2 I2S Interfaces
    • 1 16/24-bit, master/slave mode; 1 16-bit, master/slave mode with TDM
    • 2 TX/RX channels with 16/24/48/96/192 kHz and 11.025kHz, 22.05kHz, 44.1kHz frequencies
  • 5 PWM channels
  • 14 GPIOs (fast IOs, 5V-tolerant)
  • 3 channel 12-bit AUXADC

Power management

  • Integrated DC-DC
  • Power input
    • VRTC: from 1.62V to 3.63V
    • VPMU / VRF: 3.3V (+/-10%)
    • VIO*: 1.8V/2.8V/3.3V (+/-10%)
  • Off mode: <0.5μA
  • Retention mode (with RTC)
    • <2μA (RTC only)
    • ~4.4μA with 8KB RAM sleep mode
  • Deep sleep mode (with external 32kHz clock)
    • 58μA with 0KB RAM sleep mode
    • 90μA with 384KB RAM sleep mode
  • G-band RX power: 59 mA
  • G-band TX power
    • FPA:268 mA at 19 dBm CCK
    • HPA: 203 mA at 16.5 dBm OFDM
  • DTIM interval with 32kHz external clock source and 384KB SRAM
    • DTIM=1: 0.74mA
    • DTIM=3: 0.33mA
  • Ambient temperature from -40°C to 85°C

Note: The power consumption data is measured at 25°C

Clock source

  • 26MHz or 40MHz crystal oscillator

  • 32kHz crystal oscillator or internal 32kHz RC for RTC


  • 3.15-mm x 3.15-mm x 0.53-mm 56-ball WLCSP with 0.4-mm ball pitch