35 #ifndef __HAL_SPI_MASTER_H__ 36 #define __HAL_SPI_MASTER_H__ 37 #include "hal_platform.h" 39 #ifdef HAL_SPI_MASTER_MODULE_ENABLED 69 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 124 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 157 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 171 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 440 #ifdef HAL_GPIO_FEATURE_SET_DRIVING 483 #ifdef HAL_SPI_MASTER_FEATURE_ADVANCED_CONFIG 490 HAL_SPI_MASTER_LITTLE_ENDIAN = 0,
491 HAL_SPI_MASTER_BIG_ENDIAN = 1
492 } hal_spi_master_byte_order_t;
497 HAL_SPI_MASTER_CHIP_SELECT_LOW = 0,
498 HAL_SPI_MASTER_CHIP_SELECT_HIGH = 1
499 } hal_spi_master_chip_select_polarity_t;
504 HAL_SPI_MASTER_NO_GET_TICK_MODE = 0,
505 HAL_SPI_MASTER_GET_TICK_DELAY1 = 1,
506 HAL_SPI_MASTER_GET_TICK_DELAY2 = 2,
507 HAL_SPI_MASTER_GET_TICK_DELAY3 = 3,
508 HAL_SPI_MASTER_GET_TICK_DELAY4 = 4,
509 HAL_SPI_MASTER_GET_TICK_DELAY5 = 5,
510 HAL_SPI_MASTER_GET_TICK_DELAY6 = 6,
511 HAL_SPI_MASTER_GET_TICK_DELAY7 = 7
512 } hal_spi_master_get_tick_mode_t;
517 HAL_SPI_MASTER_SAMPLE_POSITIVE = 0,
518 HAL_SPI_MASTER_SAMPLE_NEGATIVE = 1
519 } hal_spi_master_sample_select_t;
523 #ifdef HAL_SPI_MASTER_FEATURE_DEASSERT_CONFIG 526 HAL_SPI_MASTER_DEASSERT_DISABLE = 0,
527 HAL_SPI_MASTER_DEASSERT_ENABLE = 1
528 } hal_spi_master_deassert_t;
532 #ifdef HAL_SPI_MASTER_FEATURE_MACRO_CONFIG 535 HAL_SPI_MASTER_MACRO_GROUP_A = 0,
536 HAL_SPI_MASTER_MACRO_GROUP_B = 1,
537 HAL_SPI_MASTER_MACRO_GROUP_C = 2
538 } hal_spi_master_macro_select_t;
541 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 544 HAL_SPI_MASTER_EVENT_SEND_FINISHED = 0,
545 HAL_SPI_MASTER_EVENT_RECEIVE_FINISHED = 1
546 } hal_spi_master_callback_event_t;
582 #ifdef HAL_SPI_MASTER_FEATURE_ADVANCED_CONFIG 585 hal_spi_master_byte_order_t byte_order;
586 hal_spi_master_chip_select_polarity_t chip_polarity;
587 hal_spi_master_get_tick_mode_t get_tick;
588 hal_spi_master_sample_select_t sample_select;
589 } hal_spi_master_advanced_config_t;
593 #ifdef HAL_SPI_MASTER_FEATURE_CHIP_SELECT_TIMING 596 uint32_t chip_select_setup_count;
600 uint32_t chip_select_hold_count;
603 uint32_t chip_select_idle_count;
606 } hal_spi_master_chip_select_timing_t;
622 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 636 typedef void (*hal_spi_master_callback_t)(hal_spi_master_callback_event_t event,
void *user_data);
703 #ifdef HAL_SPI_MASTER_FEATURE_ADVANCED_CONFIG 726 hal_spi_master_advanced_config_t *advanced_config);
750 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 817 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 879 #ifdef HAL_SPI_MASTER_FEATURE_CHIP_SELECT_TIMING 895 hal_spi_master_chip_select_timing_t chip_select_timing);
899 #ifdef HAL_SPI_MASTER_FEATURE_DEASSERT_CONFIG 915 hal_spi_master_deassert_t deassert);
919 #ifdef HAL_SPI_MASTER_FEATURE_MACRO_CONFIG 934 hal_spi_master_macro_select_t macro_select);
937 #ifdef HAL_SPI_MASTER_FEATURE_DMA_MODE 952 hal_spi_master_callback_t callback,
956 #ifdef HAL_SPI_MASTER_FEATURE_DUAL_QUAD_MODE 969 hal_spi_master_mode_t mode);
997 uint8_t command_bytes);
hal_spi_master_clock_polarity_t
SPI master clock polarity definition.
Definition: hal_platform.h:473
SPI master send and receive configuration structure.
Definition: hal_spi_master.h:611
uint8_t * send_data
Data buffer to send, this parameter cannot be NULL.
Definition: hal_spi_master.h:612
hal_spi_master_status_t hal_spi_master_init(hal_spi_master_port_t master_port, hal_spi_master_config_t *spi_config)
This function is mainly used to initialize the SPI master and set user defined common parameters like...
hal_spi_master_clock_phase_t phase
SPI master clock phase setting.
Definition: hal_spi_master.h:579
uint32_t clock_frequency
SPI master clock frequency setting.
Definition: hal_spi_master.h:575
hal_spi_master_clock_phase_t
SPI master clock format definition.
Definition: hal_platform.h:480
hal_spi_master_slave_port_t slave_port
SPI slave device selection.
Definition: hal_spi_master.h:576
hal_spi_master_slave_port_t
selection of spi slave device connected to which cs pin of spi master
Definition: hal_platform.h:466
SPI master invalid input parameter.
Definition: hal_spi_master.h:554
uint8_t * receive_buffer
Received data buffer, this parameter cannot be NULL.
Definition: hal_spi_master.h:614
SPI master is busy.
Definition: hal_spi_master.h:561
SPI master operation completed successfully.
Definition: hal_spi_master.h:555
SPI master function error occurred.
Definition: hal_spi_master.h:551
hal_spi_master_bit_order_t
SPI master transaction bit order definition.
Definition: hal_platform.h:487
hal_spi_master_status_t hal_spi_master_deinit(hal_spi_master_port_t master_port)
This function resets the SPI master, gates its clock, disables interrupts.
hal_spi_master_status_t
SPI master status.
Definition: hal_spi_master.h:550
hal_spi_master_status_t hal_spi_master_get_running_status(hal_spi_master_port_t master_port, hal_spi_master_running_status_t *running_status)
This function gets current running status of the SPI master.
SPI master configuration structure.
Definition: hal_spi_master.h:574
uint32_t send_length
The number of bytes to send, no greater than 4.
Definition: hal_spi_master.h:613
hal_spi_master_status_t hal_spi_master_send_polling(hal_spi_master_port_t master_port, uint8_t *data, uint32_t size)
This function is used to send data synchronously with FIFO mode.
hal_spi_master_clock_polarity_t polarity
SPI master clock polarity setting.
Definition: hal_spi_master.h:578
SPI master is idle.
Definition: hal_spi_master.h:562
SPI master is busy.
Definition: hal_spi_master.h:552
hal_spi_master_running_status_t
SPI master running status.
Definition: hal_spi_master.h:560
hal_spi_master_port_t
This enum defines the SPI master port.
Definition: hal_platform.h:459
hal_spi_master_bit_order_t bit_order
SPI master bit order setting.
Definition: hal_spi_master.h:577
uint32_t receive_length
The valid number of bytes received with the number of bytes to send.
Definition: hal_spi_master.h:615
SPI master invalid port.
Definition: hal_spi_master.h:553
hal_spi_master_status_t hal_spi_master_send_and_receive_polling(hal_spi_master_port_t master_port, hal_spi_master_send_and_receive_config_t *spi_send_and_receive_config)
This function simultaneously sends and receives data in the FIFO mode.